Junction field effect transistors (JFETs) in integrated circuits (ICs) provide a low noise current modulation capability that is important for many analog circuits. The JFET pinch-off voltage, analogous to the threshold voltage of a metal oxide semiconductor (MOS) transistor, decreases as gate junction spacing decreases, which in turn decreases the JFET maximum drain voltage. Thus, pinch-off voltage is commonly balanced against the maximum drain voltage in circuit performance. Moreover, pinch-off voltage and maximum drain voltage depend on diffused junction depths, and exhibit consequential variability across an IC, and from IC to IC.